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A Novel Power Management Save-Restore Flow Architecture using Calibrated Ring Oscillator Clock Generation

机译:使用校准的环形振荡器时钟生成的新型电源管理保存-恢复流程架构

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This paper deals with the issue of system wake up latency as a consequence of power gating techniques. There are different architectures proposed to reduce the power inside the IPs (Intellectual property) like clock gating and power gating, Still system level IDLE power gating is a bigger concern. According to the nature of the system, multiple system states are created based on power and IDLE conditions. Another drawback of the power gating is system wake up latency which will be impacting the system performance. Here in this paper we have introduced an innovative way to reduce the system latency by a new power architecture flow with a calibrated ring oscillator clock and ran all power management operations on the newly generated clock. The overall impact in performance, power and area will also be discussed in this paper.
机译:本文讨论了由于电源门控技术而导致的系统唤醒延迟问题。为了降低IP(知识产权)内部的功耗,提出了多种架构,例如时钟门控和电源门控。系统级IDLE电源门控仍然是一个更大的问题。根据系统的性质,基于电源和空闲状态创建多个系统状态。电源门控的另一个缺点是系统唤醒延迟,这将影响系统性能。在本文中,我们介绍了一种创新的方法,可通过带有校准的环形振荡器时钟的新电源架构流程来减少系统等待时间,并在新生成的时钟上运行所有电源管理操作。本文还将讨论对性能,功耗和面积的总体影响。

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