The Technique of Fast Power Analysis for FinFET Standard Cells

摘要

The rapid development of FinFET technology in recent years has led to modifications of digital design flow at all stages. Quantization of the channel width of the transistor led to changes in approaches to circuit and layout design of digital standard cells. The discrete formation of the transistor channel width, set by the number of “fins”, led to the need to create the new analytical models of the basic parameters of standard cells. The paper considers the technique of fast power analysis of standard cells of FinFET, that involves the introduction of some empiric coefficients for a specific technology. The technique allows quickly to estimate the power consumption of digital standard cells based on FinFET with regard to cell layout when changing the number of “fins”. The paper presents the results of efficiency analysis of developed technique for 7nm technology.