Four-Terminal FinFET Device Technology

摘要

One of the biggest challenges for the VLSI circuits with 32-nm-technology nodes and beyond is to overcome the issue of catastrophic increases in power consumption due to short-channel effects (SCEs). Fortunately, "independent" double-gate (DG) FinFETs (named "4-terminal-FinFET" because of its four terminals; source, drain, gate 1 and gate 2) have a promising potential to overcome this issue thanks to a post-fabrication flexible Vth controllability in addition to their superior SCE immunity. This paper presents novel 4T-FinFET device technology based on experimental demonstrations. Newly-developed DG separation processes for the 4T-FinFETs, successful fabrication of the optimum 4T-FinFET with asymmetric gate oxides, and dynamic power management demonstration using 4T-FinFET are presented.