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LRCG: Latch-based Random Clock-Gating for Preventing Power Analysis Side-Channel Attacks

机译:LRCG:基于锁存的随机时钟门控,用于防止功率分析侧通道攻击

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This paper proposes a new ASIC design flow using latch retiming and random clock-gating to cope with power analysis side-channel attacks. We cast the side-channel attack problem as a combination of retiming and clock-gating problems and solve the problems using only existing EDA tool chains. In particular, we achieve light weight time-shifting obfus-cation against DPA (Differential Power Analysis) and CPA (Correlation Power Analysis) attacks by changing when to latch randomly. Our proposed LRCG (Latch-based Random Clock-Gating) method incurs only 13% of hardware area overhead that is significantly smaller than other balancing and masking countermeasures which require 100% and 294% overhead, respectively. Our experimental results show that LRCG incurs only negligible performance and energy consumption penalty, while successfully preventing DPA and CPA attacks in all cases.
机译:本文提出了一种新的ASIC设计流程,该流程使用锁存重定时和随机时钟门控来应对功耗分析侧信道攻击。我们将边信道攻击问题视为重定时和时钟门控问题的组合,并仅使用现有的EDA工具链来解决问题。特别是,我们通过更改随机锁存的时间来实现针对DPA(差分功率分析)和CPA(相关功率分析)攻击的轻量级时移模糊处理。我们提出的LRCG(基于锁存的随机时钟门控)方法仅产生了13%的硬件区域开销,该开销明显小于其他分别需要100%和294%开销的平衡和屏蔽对策。我们的实验结果表明,LRCG仅会产生微不足道的性能和能耗损失,而在所有情况下都能成功防止DPA和CPA攻击。

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