LRCG: Latch-based Random Clock-Gating for Preventing Power Analysis Side-Channel Attacks

摘要

This paper proposes a new ASIC design flow using latch retiming and random clock-gating to cope with power analysis side-channel attacks. We cast the side-channel attack problem as a combination of retiming and clock-gating problems and solve the problems using only existing EDA tool chains. In particular, we achieve light weight time-shifting obfus-cation against DPA (Differential Power Analysis) and CPA (Correlation Power Analysis) attacks by changing when to latch randomly. Our proposed LRCG (Latch-based Random Clock-Gating) method incurs only 13% of hardware area overhead that is significantly smaller than other balancing and masking countermeasures which require 100% and 294% overhead, respectively. Our experimental results show that LRCG incurs only negligible performance and energy consumption penalty, while successfully preventing DPA and CPA attacks in all cases.