Lead-Free Assembly Reliability of Fine Pitch Wafer Level CSPs

摘要

Production yields and the long-term reliability of fine pitch area array packaging are much more sensitive to assembly parameters than larger pitch devices. The following paper discusses the effects of stencil design, paste printing versus flux dipping processes, and reflow ambient on the assembly yields and thermal cyclic reliability of commercially available lead-free and SnPb 0.4 and 0.5mm pitch wafer level chip scale packages (WLCSP). Optimum process designs are offered for each device and alternate package dimensions are presented that may produce desirable reliability requirements for most consumer applications.