Process Variability-Induced Timing Failures - A Challenge in Nanometer CMOS Low-Power Design

摘要

Intro-die random process variability-induced timing failure is one of the biggest challenges in today's low-power CMOS designs. For the first time, this work examined the effects of the variability on circuit functionality, yield, and voltage scaling. A simple yet effective method for quantifying the effects of the variability on digital timing, the DOS chart, was introduced. The variability causes timing skews which in turn cause circuit failures and yield loss at low voltages. This new failure mode is statistical in nature and behaves differently from traditional timing failures. It has a different worst-case corner that requires further statistical analysis. We presented a variability-resilient design and verification methodology that deals with this new failure.