HIGH PERFORMACE STRAINED-SOI CMOSFETs

摘要

Strained-Si-On-Insulator (strained-SOI) CMOS is a promising device structure for satisfying requirements of both high current drive and low V_(dd) under sub-100 nm nodes, because of the combination of advantages of SOI MOSFETs and high mobility strained-Si channels. In this paper, we present the concept, the device structures and the fabrication techniques of strained-SOI CMOS and demonstrate the high performance of strained-SOI CMOS devices. It is shown that strained-SOI CMOS ring oscillators successfully operate with the performance enhancement of 30-70% against conventional SOI CMOS ones. We also propose a new fabrication method of strained-SOI substrates, called the Ge condensation technique. Several new ideas on the fabrication of strained-SOI substrates based on this technique are introduced and the experimental results are presented.