Nonlinear block latency insertion method for fast simulation of strongly coupled network with CMOS inverters

摘要

For an analysis of large networks including nonlinear active devices and coupled elements, conventional SPICE-like simulators suffer from a large amount of computational cost due to time-consuming direct matrix operations. In order to overcome the problem, the block-latency insertion method (block-LIM) has been proposed as a fast circuit simulation technique. The advantage of the block-LIM is employing a local matrix operation. However, there are few applications of the block-LIM to the nonlinear circuit simulation. In this paper, we describe an efficient nonlinear circuit simulation technique by using a nonlinear version of block-LIM, and estimate its characteristics by analyzing to some example nonlinear circuits.