首页> 外文会议>Electrical and Computer Engineering, 2009. CCECE '09 >A programmable pre-cursor ISI equalization circuit for high-speed serial link over highly lossy backplane channel
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A programmable pre-cursor ISI equalization circuit for high-speed serial link over highly lossy backplane channel

机译:用于高损耗背板通道上的高速串行链路的可编程前驱ISI均衡电路

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This paper presents a programmable pre-cursor ISI equalization circuit for high-speed serial data transmission over highly lossy electrical backplane channels. Although decision-feedback-equalizer (DFE) provides an effective way to compensate various channel impairments, such as frequency dependent loss, dispersion and reflections in the legacy backplane environment, for high-speed, highly lossy band-limited channel, the pre-cursor inter-symbol interference (ISI) is still a significant problem for channel equalization. A programmable pre-cursor ISI equalizer combined with a 3-tap DFE is implemented to work at 10-Gb/s and compensate the channel loss of -20 dB. The results show it outperform a traditional 5-tap DFE.
机译:本文提出了一种可编程的前体ISI均衡电路,用于在高损耗电底板通道上进行高速串行数据传输。尽管决策反馈均衡器(DFE)提供了一种有效的方法来补偿各种信道损伤,例如与频率有关的损耗,色散和传统背板环境中的反射,但对于高速,高损耗的带宽受限的信道而言,前兆符号间干扰(ISI)仍然是信道均衡的重要问题。结合3抽头DFE的可编程前驱ISI均衡器可以以10 Gb / s的速度工作并补偿-20 dB的信道损耗。结果表明它优于传统的5抽头DFE。

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