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Facilitating the Design of Fault Tolerance in Transaction Level SystemC Programs

机译:简化事务级别SystemC程序中的容错设计

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Due to their increasing complexity, today's SoC (System on Chip) systems are subject to a variety of faults (e.g., soft errors, component crash, etc.), thereby making fault tolerance a highly important property of such systems. However, designing fault tolerance is a complex task in part due to the large scale of integration of SoC systems and different levels of abstraction provided by modern system design languages such as SystemC. Most existing methods enable fault injection and impact analysis as a means for increasing design dependability. Nonetheless, such methods provide little support for designing fault tolerance. To facilitate the design of fault tolerance in SoC systems, this paper propose an approach where fault tolerance is designed at the level of inter-component communication protocols in SystemC Transaction Level (TL) models. The proposed method includes four main steps, namely model extraction, fault modeling, addition of fault tolerance and refinement of synthesized fault tolerance to SystemC code. We demonstrate the proposed approach using a simple SystemC transaction level program that is subject to communication faults. We also provide a roadmap for future research at the intersection of fault tolerance and hardware-software co-design.
机译:由于它们的复杂性不断增加,当今的SoC(片上系统)系统会遇到各种故障(例如,软错误,组件崩溃等),从而使容错成为此类系统的重要属性。但是,设计容错能力是一项复杂的任务,部分原因是SoC系统的大规模集成以及现代系统设计语言(例如SystemC)提供的不同抽象级别。现有的大多数方法都可以将故障注入和影响分析作为提高设计可靠性的一种手段。但是,这样的方法为设计容错提供了很少的支持。为了方便SoC系统中的容错设计,本文提出了一种在SystemC事务级别(TL)模型中的组件间通信协议级别上设计容错能力的方法。所提出的方法包括四个主要步骤,即模型提取,故障建模,增加容错能力和完善对SystemC代码的综合容错能力。我们使用受通信故障影响的简单SystemC事务级别程序演示了所建议的方法。我们还为容错与软硬件协同设计的交叉点提供了未来研究的路线图。

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