Advanced TSV Copper Electrodeposition for 3D Interconnect Applications

摘要

Robust and manufacturable processes are needed to enable a smoother and faster transferrnof TSV technology from development to production.rnThere are several steps involved with TSV technology application. Either if it is donernbefore or after thinning the wafer, as a via first, middle or via last approach, the mainrnsteps are: via etching, lining with insulator/barrier and copper seed, deep via fill andrnchemical mechanical planarization (CMP), chip dicing and stacking. Deep via fill is onernof thee most critical steps in forming the TSV electrodes, and copper electrodepositionrnprocess has been identified to be the most appropriate and cost effective method of fillingrnthe vias.rnVarious critical factors with significant effect on the process performance were found:rnseed layer uniformity, via profile and size, stability and performance of the chemicals andrnequipment design. The amount and quality of the copper at the top of the vias and overrnthe entire surface of the wafer is very important for the CMP processing. A more uniformrndeposition and lower overburden could significantly decrease the complexity and cost ofrnthe CMP step. The copper thickness profile between deposition and CMP can be crossoptimizedrnto reduce dishing, increase throughput and reduce cost. This paper will focusrnon the deep via fill, the critical factors associated with this step and integration aspects ofrnCu TSV deposition step that need to be taken in consideration for successful applicationrnof this technology.rnA significant amount of work has been performed to develop processes that canrnsuccessfully fill features of various sizes in a cost effective way. Some of the chemistriesrnavailable commercially today, although have very good super-fill characteristics, have therndisadvantage of forming nodular and high-stress deposits which could have a negativernimpact on CMP processing. An innovative process with strong bottom-up capability thatrnsignificantly reduces the overburden while increasing the speed of deposition has beenrndeveloped at Semitool and the characteristics of this process and advantages overrnprevious generation processes will be presented. The effect of copper stress and copperrnextrusion observed during annealing step as well as approaches taken to minimize thisrneffect will be described.