A 1 GHz Differential 2nd-order Lowpass Sigma Delta Modulator in CMOS for Wireless Receivers

摘要

This paper presents the design of a 1 GHz continuous-time second order Lowpass Sigma Delta Modulator (LPSDM). The design is intended to meet the future requirements of wideband wireless receivers. The continuous-time Noise Transfer Function (NTF) for the modulator is realized using two G_m-C integrators with negative transconductance feedback and three linearized G_m elements. A three-stage delayed comparator is employed for designing the one bit quantizer; therefore a delayed NTF had to be synthesized. The presented target design is 0.18μm CMOS process. The designed chip uses both 3.3V and 1.8V MOSFETs and consumes 80mW including the clock driver and the output buffer. The performance of the modulator based on post layout simulation is 11bits for a 5 MHz bandwidth and 8.6 bits for an 11MHz bandwidth.