Design and analysis of fault-tolerant multistage interconnection networks with low link complexity

机译：低链路复杂度的容错多级互连网络的设计与分析

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《Annual international symposium on Computer architecture;International symposium on Computer architecture》|1985年|P.376-386|共11页
会议地点 Boston MA(US);Boston MA(US)
作者
V. P. Kumar; S. M. Reddy; PV. P. Kumar; PS. M. Reddy;
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Department of Electrical and Computer Engineering University of Iowa Iowa City Iowa;

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Design and analysis of fault-tolerant multistage interconnection networks with low link complexity

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