Can Stochastic Modelling and Analysis of Multistage Interconnection Networks Lead to Efficient Usage of Redundancy for Fault-Tolerant Design.

摘要

The rapid growth in device density achieved by very large scale integration technology over the past decade had the attention of researchers centered around the design of array processors. The systolic arrays had been designed for a wide variety of applications, and consequently formal strategies for mapping algorithms onto processor arrays were developed. Use of spare or temporarily idle processing elements to achieve fault tolerance became an attractive aspect of VLSI array processing. The goal was to accomplish the designated task in case of transient or permanent failure of one or more processors, and to achieve a graceful degradation as far as possible. However, formal mapping techniques have not been extended to capture the issues of redundancy mapping. Moreover, processor interconnection topology like shuffle-exchange or butterfly networks, which require global communication links, were not considered to be practical for large on-chip design.