NEAR TERM SOLUTIONS FOR 3D PACKAGING OF HIGH PERFORMANCE DRAM

摘要

The revolution in performance driven electronic systems continues to challenge the IC packaging industry. To enable the new generations of processors to reach their performance potential many manufacturers have developed interface formats to enable greater memory bandwidth. To ensure that the memory functions are able to support the increased signal speed, package developers are relying more and more on innovative 3D package assembly techniques and process refinement. For some applications companies have had limited success in stacking die elements directly onto an interposer substrate using wire-bond processes. Stacking two or more memory die with perimeter located bond pads has been fairly successful. However, because the die elements will typically have the same physical outline, spacers are needed between layers to clear the wire-bond loop height. Additionally, overall finished package height can be critical for a number of applications. Even though the die elements can be made very thin, the accumulated elements within the stack can be excessive. High performance DRAM die are especially difficult to stack. This is due to the center positioned wire-bond pad sites. This factor has complicated the die stacking process and because of the excessively long wire-bond interface, functional signal speed is significantly degraded. Effective 3D stacking of DRAM devices can offer many benefits; improved performance, increased component density and greater surface area utilization. The methodology selected for package assembly, however, must consider process complexity, the costs associated with each process, overall package assembly yield and end product reliability. This paper will explore the positive and negative aspects of the package assembly variations noted above, comparing both performance attributes and physical limitations. Additionally, the authors will introduce a very innovative and very thin 3D package design and assembly process developed specifically for center-bond pad DRAM die. The methodology promises to remain economical because it requires no special die level process steps and utilizes the existing package assembly infrastructure.