An Efficient Write Update Cache Coherence Scheme for Widely Shared Data on Shared Memory Multiprocessors

摘要

As well known, cache coherence schemes significantly influence the overall performance of multiprocessors. Since most parallel applications show relatively long write runs for shared variables, many large-scale multiprocessors have favored the write invalidate scheme which achieve coherence by invalidating stale cache copies. Widely shared data such as synchronization variables, however, have short write runs, and thus such invalidation causes many unnecessary cache misses. But typical write update scheme usually results in too much coherence traffic under the present communication settings. This paper proposes a new broadcast switch feature, and on the feature, presents an efficient write update coherence and read-broadcast schemes which are expected to considerably reduce memory access traffic as well as cache misses for widely shared data.