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Cache coherence protocol for reducing the effects of false sharing in non- bus-based shared-memory multiprocessors
Cache coherence protocol for reducing the effects of false sharing in non- bus-based shared-memory multiprocessors
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机译:高速缓存一致性协议,用于减少基于非总线的共享内存多处理器中错误共享的影响
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摘要
A cache coherence protocol for a multiprocessor system. Each processor in the system has an associated cache capable of storing multiple word data lines. The system also includes a plurality of main memory modules, each having an associated distributed global directory storing directory information for lines stored in the associated main memory module. Each main memory module is connected to each processor by means of a multi- stage interconnection network. When a processor attempts to over-write an individual word in a line stored in its associated cache, a write request signal is sent to the appropriate global directory, and each other processor whose cache stores a copy of the line is notified of the request. When each other processor has responded with an acknowledgement, the first processor is allowed to proceed with the write.
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