SELF-INVALIDATION APPARATUS AND METHOD FOR REDUCING COHERENCE OVERHEADS IN A BUS-BASED SHARED-MEMORY MULTIPROCESSOR

摘要

PURPOSE: A self-invalidation apparatus and a method for a coherence overhead decrease of a multiprocessor are provided to decrease an invalidation traffic on a shared bus of an apparatus by providing a self-invalidation unit to each processor node. CONSTITUTION: A plurality of processors each includes a local cache. A sharing bus includes a self-invalidation line and shared line and represents a shared state for a cache block and is connected with each local cache. A display unit sets a self-invalidation line to the local processor for displaying the cache block for generating the displayed cache block. A self-invalidation unit self-invalidates the displayed cache block to each local processor. It is possible to locally invalidate the cache block without an invalidation sharing bus transaction for thereby decreasing the invalidation traffic on the sharing bus.