Ultra-Precise Low-Cost Surface Planarization Process for Advanced Packaging Fabrications and Die Assembly: A Survey of Recent Investigations on Unit Process Applications and Integrations

摘要

A suite of highly precise surface planarization equipment and associated unit process have been developed for several years. Recent studies showed that this process is suitable to address the persistent needs for improved planarity of surface topographies and bonding interfaces during advanced packaging fabrications and assembly. Myriad process capabilities have been achieved to date on both wafer-level for device die fabrications as well as on panel-level for interposer and substrate fabrications. Some planarization highlights include (i) achieving copper pillars height uniformity of less than 1.5um across entire 300mm Si low-k wafer area, (ii) being able to integrate with panel-, lamination-based RDL fabrications based on either pohto-lithography method or by direct laser patterning methods in planarizing both patterned plating features and blanket overburden layer structure, and (iii) establishing the manufacturing readiness for large panel substrate sizes.