The issue of Glitch in FPGA devices design is a universal problem that every integrate circuit designer will meet. It is discussed in some books, but not all―around enough. This paper makes a attempt to discuss this problem a little more completely. First, it is introduced that what the issue of Glitch is in combinational circuit and its coming into being. Then it is illustrated that how to solve this problem from software, hardware and new design circuit. This is the simplest and most practical method in the design to modify delay time of input end with software. Its advantage is to solve the problem quickly. Modifying circuit is mainly to use synchronization clock and input signal to be a part of D trigger input. In such way, the Glitch can be deleted. Otherwise, it is sampled during the keeping time of output signal to eliminate the effect of Glitch. Moreover, the method of using the low―pass filter is also used to wipe out the Glitch in pins of FPGA device output. It's also introduced in the new design circuit that if the output order of the counter output end is changed at this moment, the Glitch of next combinational circuit output can be deleted. And this circuit can work stably on any occasion.
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