Side Mount Package (SMP) for Ultra-High Density Memory Applications

摘要

In recent years, package stacking technology has been pursued and practiced widely in industry, mainly asrnperimeter array package on package (PoP) stacking configuration. However, the stacking quantity is limited to justrntwo. For ultra high density die stacking application such as solid state drive (SSD), there can be as many as 64 dicernassembled in limited space. For this type of application, multi-package stacking can provide practical lower costrnsolution compared to die level memory stacking by Through Silicon Via (TSV) technology. However, multi-packagernstacking technology has not yet been demonstrated in High Volume Manufacturing. Therefore, new low cost highlyrnreliable and easily manufacturable multi-package stacking concept is necessary for ultra high memory densityrnpackaging solution. In this paper, we developed side mount package (SMP) cube, which is shown to use smallerrnboard space than any of other package stacking technology. Small board space for eight or more multi-stackrnpackages is due mainly because SMP doesn’t need redistribution layer formation process for side wallrninterconnection or through mold via (TMV) formation and solder filling process, and solder joints betweenrnindividual packages.rnKey processes for SMP are; (a) Quad-Flat-No-Lead (QFN) single package build by typical die stackingrntechnology with wire bonding and die attach film (DAF). Key feature in this step is the exposed lead pad on sidernwall of the QFN package. (b) QFN package stack by polymeric adhesive layer with thickness of 20～50 um, (c) therneight QFN package stack up by adhesive layer and the exposed pad is aligned on one area of the package stack up.rnThis array of the exposed pad from each QFN pad is naturally redistributed pad to the sidewall. (d) Final step isrnsolder ball attach process on the exposed pad array for board level interconnection. We demonstrated ultra-highrndensity package stacking solution by novel package interconnect structure, side mount package and the board levelrninterconnection by solder arrays on the sidewall of the package cube.