首页> 外文会议>42nd international symposium on microelectronics (IMAPS 2009) >An Interconnection Verification Method and a New Substrate Option for Cu Pillar Flip-chip Module Applications
【24h】

An Interconnection Verification Method and a New Substrate Option for Cu Pillar Flip-chip Module Applications

机译:铜柱倒装芯片模块应用的互连验证方法和新的基板选项

获取原文
获取原文并翻译 | 示例
获取外文期刊封面目录资料

摘要

Cu pillar flip-chip technology has been in development and production for several years. It has clearrnadvantages over solder flip chip. These advantages include fine pitch capability, flexible bump shape, and shortrnthermal/electrical path. Challenges in the assembly process are also well known. This paper introduces an easy andrneffective test method to verify the interconnection quality between Cu pillar flip chip and substrates for a volumernproduction environment. Qualification lots using this process were built and passed a full range of reliability tests.rnThe reliability of the Cu pillar flip-chip modules that were assembled on Au surface finish substrates was alsornevaluated. The study shows the feasibility of a low cost option to assemble flip chip and wire bond die on the samernsubstrate.
机译:铜柱倒装芯片技术已经开发和生产了几年。它比焊料倒装芯片具有明显的优势。这些优点包括良好的节距能力,灵活的凸块形状和较短的热/电路径。组装过程中的挑战也是众所周知的。本文介绍了一种简便有效的测试方法,以验证量产环境中铜柱倒装芯片与基板之间的互连质量。建立了使用该过程的合格批次,并通过了全面的可靠性测试。rn还评估了在Au表面精加工基板上组装的Cu柱倒装芯片模块的可靠性。研究表明,在同一基板上装配倒装芯片和引线键合芯片的低成本选择方案是可行的。

著录项

相似文献

  • 外文文献
  • 中文文献
  • 专利
获取原文

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号