Delay analysis and design exploration for 3D SRAM

摘要

The emerging three-dimension (3D) integration technology provides a solution to reduce delay in SRAM. In this paper, we present a physical based delay analysis approach to explore 3D SRAM design options. Our analysis can be used to optimize the 3D SRAM timing performance at both sub-array and system level. Design examples based on the MITLL 3D process are constructed to demonstrate the trade-offs. As the analysis results show, the optimized 3D sub-array provides up to 20% extra improvement for SRAM access time reduction.