A skew tolerant CMOS level-based ATM data-recovery system withoutPLL topology

摘要

In high-speed communication systems with multiple inputs fromndifferent origins, all data have to be retimed to the clock of the DSP.nThis paper describes a data-recovery system which allows a 25% tolerancenon the absolute position of the edge. The intelligent sample selectornwith memory-function retrieves the correct data from the multisampledninput, even under the circumstances of wander, clock- and data-jitternand propagation phase-shift. The used approach does not require a PLLnnor a DLL, since the straightforward mechanism results in the capture ofnthe transmitted data with only the use of the central clock of the DSP.nThe retiming is done already at the first level-change and further atneach following level-change. The good results are proven withnmeasurements on a realisation with standard cells in a standard 0.7nμm CMOS technology