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Skewed CMOS: noise-tolerant high-performance low-power static circuit family

机译:偏斜CMOS:耐噪声的高性能低功耗静态电路系列

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摘要

In this paper, we present a noise-tolerant high-performance static circuit family suitable for low-voltage operation called skewed logic. Skewed logic circuits in comparison with Domino logic have better scalability and are more suitable for low voltage applications because of better noise margins. Skewed logic and its variations have been compared with Domino logic in terms of delay, power, and dynamic noise margin. A design methodology for skewed CMOS pipelined circuits has been developed. To demonstrate the applicability of the proposed logic style, 0.35 /spl mu/m 5.56 ns CMOS 16/spl times/16 bit multipliers have been designed using skewed logic circuits and fabricated through MOSIS. Measurement results show that the multiplier only consumed a power of 195 mW due to its low clock load.
机译:在本文中,我们提出了一种适用于低电压操作的耐噪声高性能静态电路系列,称为偏斜逻辑。与Domino逻辑相比,偏斜逻辑电路具有更好的可伸缩性,并且由于具有更好的噪声容限,因此更适合于低压应用。偏斜逻辑及其变化已在延迟,功耗和动态噪声容限方面与Domino逻辑进行了比较。已经开发出用于偏斜CMOS流水线电路的设计方法。为了证明所提出的逻辑样式的适用性,使用偏斜逻辑电路设计了0.35 / spl mu / m 5.56 ns CMOS 16 / spl times / 16 bit乘法器,并通过MOSIS进行了制作。测量结果表明,该乘法器由于其低时钟负载而仅消耗了195 mW的功率。

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