Blocker-Tolerant Integrated Tunable Filters in CMOS for Next Generation Wireless Communication

摘要

Modern wireless communication standards support numerous frequency bands. A dedicated surface acoustic wave (SAW) filter is assigned to each single band to isolate the desired frequency bands. As a result, multiple SAW filters are necessary to cover different frequency bands which clearly increases cost and form factor. There is a strong demand towards complete integrated solutions to reduce the cost and form-factor of wireless devices. However, it is quite challenging to build integrated high-performance bandpass filters. The inherent losses associated with on-chip inductors lead to filters having relatively high insertion losses, limited dynamic range and low out-of-band rejection. For this reason, nowadays, most wireless systems utilize individual off-chip filters rather than fully integrated bandpass filters.;A cellular radio receiver is required to recover a weak desired signal in presence of other in-band and out-of-band interfering signals (blockers). These interfering signals near the desired signal need to be suppressed. To that end, a band selection filter is used to provide attenuation for out-of-band signals, and a subsequent baseband lowpass channel select filters provide channel selection. Existing filters providing channel selection directly at RF for cellular applications does not have adequate rejection in the stopband to full LTE requirements. In this thesis, several techniques based on N-path filters have been proposed to handle large out-of-band blockers. The ultimate rejection of classical N-path filter is limited due to non-zero switch resistance. A cascaded configuration of bandpass (BP) and bandstop (BS) filter is utilized to create notches on both sides of the passband where the center frequency of bandstop filters are shifted by using feed-forward and feedback gm cell. The filter is tunable from 0.2 GHz to 1.8 GHz. The proposed tunable filter has 48.3 dB rejection at 20 MHz offset and has 58.8 dB rejection at 45 MHz offset from the center frequency. The simulated stop-band rejection of the filter is 71.2 dB. However, it is difficult to create nearby notches without affecting the passband response of the later. To overcome the above difficulty, a new architecture is presented based on two-path signal cancellation technique to create notches close to the passband to handle large blockers. The filter consists of a tunable BPF in parallel with tunable BS filters. Due to the subtraction of BP and BS filters two notches can be created. This combination ensures the correct amplitude and phase relationships across a wide tuning range to create adjustable TZs without sacrificing the gain of the passband. This paper presents in detail the design considerations and guidelines, as well as analysis of the filter performance in the presence of non-idealities such as parasitics and imperfect clock signal shape. The proposed filter is implemented with high-Q N-path filter blocks in a 65-nm CMOS process. The passband of the filter is tunable from 0.1 GHz to 1.4 GHz with a 3-dB bandwidth of 9.8-10.2 MHz, a gain of 21.5-24 dB, a noise figure of 3-4.2 dB, and a total power consumption of 50-73 mW. TZs are created on both sides of the passband with a minimal offset of 25 MHz and are tunable across a 20 MHz range with up to 60 dB rejection. The measured blocker 1-dB compression point is 8 dBm and the out-of-band IIP3 is 23 dBm. The reported filter provides a promising on-chip filtering solution for multi-standard, multi-frequency software-defined radio applications with improved interference mitigation capabilities.;Various on-chip techniques to handle out-of-band blockers have been proposed recently. Although these approaches are suitable for suppressing a single frequency blocker, the created single-frequency notch is not effective in presence of wideband blockers which is becoming more prevalent with the development in high-speed wireless communications. A tunable active bandpass filter with bandwidth-adjustable notches close to the passband for wideband blocker suppression with high attenuation is designed and fabricated. The proposed filter is composed of a 3-pole N-path bandstop filter in cascade with an Npath bandpass filter, where the center frequency of the bandpass filter is offset from the bandstop filters. With proper tuning of the coupling capacitors in the bandstop filter, three adjacent notches can be created which provides a larger suppression bandwidth. An implementation of the filter in 65-nm CMOS exhibits a passband tunable between 0.1-1.1 GHz, with a 3-dB bandwidth of 12.4-14.2 MHz, a gain of 9.5-10.3 dB, a noise figure of 4.3-5.8 dB, and a total power consumption of 40-64.3mW. The blocker 1-dB compression point is 6.5 dBm and the out-of-band IIP3 is 18.4 dBm.