首页> 外文会议>27th European Solid-State Circuits Conference, Sep 18-20, 2001, Villach, Austria >A Wide-band, Compact, Fully Differential Highly Accurate Integrated Phase Quadrature Locked Loop on 0.18μm CMOS
【24h】

A Wide-band, Compact, Fully Differential Highly Accurate Integrated Phase Quadrature Locked Loop on 0.18μm CMOS

机译:在0.18μmCMOS上的宽带,紧凑,全差分和高精度集成相位正交锁相环

获取原文
获取原文并翻译 | 示例

摘要

A highly accurate phase quadrature locked loop (IQPLL) has been developed on a 0.18 μm CMOS process. From two differential signals provided by a local oscillator LO, whose phases are roughly in quadrature, the IQPLL circuit generates accurate 0, 90, 180 & 270°phase shifted square signals. For the full 900-2300MHz frequency range, IQPLL achieves an output quadrature phase error of less than 0.25°for an input quadrature phase error of at least +-5°. IQPLL is completely integrated (including voltage and current references), features 0.08mm~2 and consumes 15.8mW at 1.8V, which is mainly due to the 2.3GHz CML cells. When implemented after the local oscillator, within the IQPLL bandwidth this circuit also improves the total output phase noise by 3dB on each output signal, and the differential phase noise is rejected by 20dB/decade.
机译:在0.18μmCMOS工艺上开发出了高精度的正交锁相环(IQPLL)。 IQPLL电路从相位大约为正交的本地振荡器LO提供的两个差分信号中,生成精确的0、90、180和270°相移平方信号。对于900-2300MHz的整个频率范围,IQPLL的输出正交相位误差小于0.25°,而输入正交相位误差至少为+ -5°。 IQPLL完全集成(包括电压和电流基准),功能为0.08mm〜2,在1.8V时功耗为15.8mW,这主要归功于2.3GHz CML单元。当在本地振荡器之后实施时,在IQPLL带宽内,该电路还将每个输出信号上的总输出相位噪声提高了3dB,并且差分相位噪声被抑制了20dB /十倍频程。

著录项

相似文献

  • 外文文献
  • 中文文献
  • 专利
获取原文

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号