Analysis of the Floating Voltage Transfer Characteristic and Comparison of Circuit Styles in Partially Depleted SOI-CMOS

摘要

Hysteretic behavior of PD-SOI devices is a major challenge for circuit designers. It arises from the floating body and affects a number of properties critical to circuit performance such as propagation delay, switching behavior and noise margins. The concept of floating β has been proposed in the literature to describe the hysteretic behavior of the voltage transfer characteristic, but a detailed analysis of this idea and other transfer characteristic related issues in PD-SOI is lacking in the literature. In this paper, we have analyzed the transient voltage transfer characteristic of PD-SOI circuits in detail and have related that to the concept of floating β ratio. We have also evaluated circuit techniques proposed for PD-SOI in the light of these findings and have made appropriate recommendations for circuit design in PD-SOI.