首页> 外文会议>27th European Solid-State Circuits Conference, Sep 18-20, 2001, Villach, Austria >A GSM RECEIVER BASE BAND IN 0.25μ, 1.8V FULLY DEPLETED SOI INCLUDING A 4th ORDER SERIAL ΣΔ A/D CONVERTER
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A GSM RECEIVER BASE BAND IN 0.25μ, 1.8V FULLY DEPLETED SOI INCLUDING A 4th ORDER SERIAL ΣΔ A/D CONVERTER

机译:具有0.25μ,1.8V全耗尽SOI的GSM接收器基带,包括四阶串行ΣΔA / D转换器

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摘要

SOI technology is very promising for digital low voltage low power devices, but radio integration requires also the base band analog and the RF circuits to be realised in the same technology for a single chip radio. In the analog circuits we learn to live with the kink effect and in the RF we benefit from the low drain&source to bulk capacitance. In this paper we report the obstacles encountered in the base band analog design for a GSM receiver and the 4th order serial sigma delta architecture. Index terms-SOI, GSM, filters, switched capacitor, sigma delta converter.
机译:SOI技术对于数字低电压低功耗设备非常有前途,但是无线电集成还要求基带模拟和RF电路必须以同一技术实现,以实现单芯片无线电。在模拟电路中,我们学会忍受扭结效应;在射频中,我们受益于低漏源和大电容。在本文中,我们报告了在GSM接收机的基带模拟设计和4阶串行sigma delta架构中遇到的障碍。索引项-SOI,GSM,滤波器,开关电容器,sigma delta转换器。

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