Design of Low Power 8-Bit DAC Using PTM-LP Technology

摘要

With emerging high performance digital circuits, the need for data converters with high accuracy, high speed and low power for various kinds of applications has increased greatly. Extensive researches are being conducted in order to decrease the size of data converters to obtain low power and high speed characteristics. Digital to Analog Converters (DACs) convert digital signals to analog signals. This paper presents the design of a low power, 8-bit, segmented current steering DAC using PTM 32nm technology. The simulation was carried out in LTSpice software. The DNL and INL of the converter was measured to be 0.37 LSB and 1.5 LSB respectively. With an input date rate of 1GHz, the SFDR was measured to be 33dB. The total power consumption of the converter was 0.257mW. The same design was simulated with PTM 16nm technology and results were compared with each other and other recent works.