Optimizing routing network of shared hardware design for multiple application circuits

摘要

A previously proposed technique “Application Specific Inflexible FPGA (ASIF)” presented a method to generate an optimized hardware design for a set of application circuits. This design can execute multiple application circuits but one at a time. An ASIF is generated by significantly optimizing the routing resources of Field Programmable Gate Array (FPGA). But still the design has many avenues for the optimization which was not taken under consideration in previous design. Therefore, in this work we explore different techniques to optimize the design. We termed it as “ASIF++”. Experiments reveal that ASIF++ is 4% ~ 15% smaller than the ASIF whereas ASIF++ is 73% ~ 80% smaller than its corresponding FPGA.