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Design of QCA circuits using new 1D clocking scheme

机译:使用新的一维时钟方案设计QCA电路

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摘要

This paper considers the proposed clocking scheme for Quantum-dot Cellular Automata (QCA) designs; this scheme utilizes only single or regular (90n0n) cells for circuit design. Based on the analysis of previous schemes, use of single (regular) cells rather than both regular and rotated cells is believed to be an important idea for the QCA designs. According to the previous clocking schemes there are no such schemes exist where only single phase cells are used for circuit design. The main drawback of the previous schemes is that during the fabrication, there is a possibility of “cross-coupling” between the two wires of 90n0nand 45n0n, when arrangement of any cells is misaligned. But there is no misalignment when only single cells are used. The proposed scheme is based on 1D clocking scheme and aim is to provide crossing and information flow with only single or regular cells. Some Combinational circuits such as Adders Half adder, Full adder, 2-Bit adder and 4-Bit adder are designed using proposed 1D clocking scheme with only regular cells (90n0n). It is observed that the circuits designed using this proposed clocking scheme achieves same results in comparisions to the best previous relavant works. Simulation and Verification are carried out by QCADesigner.
机译:本文考虑了为量子点元胞自动机(QCA)设计提出的时钟方案。此方案仅使用单个或常规(90n 0 n)个单元用于电路设计。基于对先前方案的分析,对于QCA设计,使用单个(常规)单元而不是常规和旋转单元被认为是重要的想法。根据先前的时钟方案,在仅单相单元用于电路设计的情况下不存在这样的方案。先前方案的主要缺点是在制造过程中,在90n 0 nand 45n 0 n。但是,仅使用单个单元格时就不会出现未对齐的情况。所提出的方案基于一维时钟方案,并且目的是仅利用单个或规则单元来提供交叉和信息流。一些组合电路,例如加法器,半加法器,全加法器,2位加法器和4位加法器,是使用建议的1D时钟方案设计的,只采用常规单元(90n 0 n)。可以看出,使用该提议的时钟方案设计的电路与以前最好的相关工作相比,取得了相同的结果。仿真和验证由QCADesigner进行。

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