Modified lifting scheme algorithm for DWT with optimized latency throughput and FPGA implementation for low power area

摘要

The image processing applications require low power and high speed, the convolution based 1D-DWT is not desirable. In this proposed architecture the modified 5/3 lifting algorithm is realized on FPGA platform with optimizations. The latency and throughput is optimized with the modified algorithm. The architecture is modelled using HDL and implemented on FPGA. The proposal operates at 178MHz and realised for an area consumption of less than 1% with 24mW power consumption. The computed reports show performance improvement over existing techniques.