超高吞吐量MD5算法的FPGA实现

摘要

In this paper, a novel architecture is proposed to increase the performance of MD5 computing in FPGA , which can achieve a super-high throughput. The scheme is based on full-pipeline for MD5 implementation. Moreover, FIFO cache structure is used for data storage and cooperative computing. The results of simulation and implementation show that the scheme can achieve the theoretical upper bound on throughput. And based on the same platform of FPGA, it outperforms the published scheme with best performance in terms of 77% higher throughput.%为了提高MD5算法在FPGA中实现的运算效率,使之达到超高的数据吞吐量,提出了一种新的全流水线架构,用于实现MD5算法.架构中使用了FIFO缓存存储数据,以配合流水线的运算.实验验证其达到了单个MD5运算单元运算吞吐量的理论上限,在相同芯片平台上,超过已发表的MD5运算模块最高吞吐量的77％.