A 2nd order fully-passive noise-shaping SAR ADC with embedded passive gain

摘要

An opamp-free solution to implement 2nd order noise shaping in a successive approximation register analog-to-digital converter is presented. This 2nd order fully-passive noise shaping, which has high power efficiency, is realized by charge-redistribution. A gain of 2 is required in this proposal which is realized by a passive method to save power. A prototype chip is fabricated in a 65-nm CMOS process occupying a core area of 0.0129 mm2. An ENOB of 10.5-bit is achieved at 64-MHz sampling frequency based on an 8-bit CDAC architecture when the OSR is 4. It dissipates 252.9 μW from a 1.0-V supply and achieves a Walden FoM of 10.9 fJ/conv.-step and a Schreier FoM of 169.9 dB.