An optimized fully-passive noise-shaping SAR ADC with integration capacitor reuse technique

摘要

This paper presents an optimized Fully-Passive Noise-Shaping Successive Approximation Register (FPNS-SAR) Analog-to-Digital Converter (ADC) with passive gain and integration capacitor reuse techniques. Instead of using multi-input-pair comparator with active gain in traditional Cascaded Integrator Feed-Forward (CIFF) structure, 1-input-pair comparator with passive gain is adopted in this paper to reduce power consumption and kick-back noise. The proposed FPNS-SAR ADC was implemented with standard 65-nm CMOS process. With the oversampling ratio (OSR) of 8, the simulation results realize 79.3dB peak SNDR and 94dB peak SFDR at 6.25MHz input signal bandwidth and 100MHz sampling frequency. The proposed ADC consumes 1.245mW at 1.2V supply voltage. The calculated FOMw and FOMs are 13.2fJ/conv.-step and 176.3dB, respectively.