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Successive approximation register (SAR) analog-to-digital converter (ADC) with passive gain scaling
Successive approximation register (SAR) analog-to-digital converter (ADC) with passive gain scaling
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机译:具有无源增益定标的逐次逼近寄存器(SAR)模数转换器(ADC)
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摘要
Certain aspects of the present disclosure provide a successive approximation register (SAR) analog-to-digital converter (ADC) implemented with a passive gain scaling architecture. Certain aspects provide a circuit for analog-to-digital conversion. The circuit generally includes a plurality of capacitive elements, a plurality of switches coupled to the plurality of capacitive elements, and SAR logic having an output coupled to control inputs of the plurality of switches. The circuit also includes a comparator having an output coupled to an input of the SAR logic, a sampling circuit coupled to an input node of the circuit, and a first capacitive element coupled in series between the sampling circuit and the plurality of capacitive elements.
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