Performance enhancement and reduction of short channel effects of nano-MOSFET by using graded channel engineering

摘要

The effect of the structure on electrical parameters of short channel Double-Gate Metal-Oxide-Semiconductor Field-Effect Transistors (DG MOSFETs) has been explored. To quantitatively assess the nanoscale DG MOSFET's characteristics, the On current(Ion), Off current (Ioff), Sub threshold Swing (SS), Threshold voltage (Vth), and Drain-Induced Barrier Lowering (DIBL) are numerically calculated for the device with different channel length (L). Based on our two dimensional simulation, it is found that, to get optimum device characteristics and suppress short channel effects (SCEs) of nanoscale DG MOSFETs, tsi and tox should be simultaneously scaled down with respect to L. Even if it gives good results for Vth, the device suffers for high DIBL, SS and Ioff. To suppress further these parameters, channel engineering technique is used followed by reducing the doping concentration of Source and Drain(S/D). The parameter extraction and simulation have been done by using the commercially available device simulation software ATLAS.