Analog Sensor Based Testing of Phase-Locked Loop Dynamic Performance Parameters

摘要

Phase-locked loops are used to synthesize frequency sources for RF conversion and IO clocks for data synchronization, and serve as core building blocks for communication systems. Consequently, testing of PLL loop performance is critical for guaranteeing the reliability of the underlying communication systems. In this paper, a testing method based on loop triggering and use of low-cost built-in analog sensors (small number of transistors) to accurately predict phase-locked loop dynamic parameters is proposed. The sensors are designed in such a way that the sensor responses show strong statistical correlation with the PLL parameters being tested. Accordingly, supervised learners are "trained" to predict the required PLL parameters from the observed sensor response. A PLL is designed and simulated in closed loop over PVT corners in order to validate the testing mechanism. Parameters including charge pump current, VCO gain, bandwidth, phase margin, and locking time are predicted accurately and concurrently over these PVT corners to prove the viability of the proposed test method.