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Process characterization of highly conductive silver paste die attach materials for thin die on QFN

机译:QFN上用于薄芯片的高导电性银浆芯片附着材料的工艺表征

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In this paper, die attach process characterization on two type of highly conductive silver paste die attach materials was discussed. The first silver paste die attach materials (DA1) was used as a reference which is silver-loaded epoxy adhesive with high thermal conductivity of 60W/mK and electrical conductivity of 16Ms/m. Second silver paste die attach material (DA2) can be sintered with low pressure or pressure-less at temperature of 220°C to 280°C. DA2 material acquires high thermal conductivity range of 100–170W/mK and electrical conductivity range of 12–15Ms/m. Process specifications were set at die tilt < 1%, average bond line thickness between 25μm to 50μm and full die attach materials coverage without overflow of materials on top of die's surface. Process was optimized with 70μm thin silicon daisy chain chip with die size of 5mm×5mm on Ag plated QFN lead frame for both silver paste materials and achieved the required process specifications. Process optimized on DA1 achieved average bond line thickness ranged from 24.5μm to 30.5μm with die tilt less than 0.24% and DA2 had average bond line thickness ranged from 32.6μm to 44.2 μm with die tilt less than 0.15%. There was further evaluation on die attach process with silver sintered paste for different die thickness (which 50μm, 70μm and 175μm were used) on a fixed die size of 5mm×5mm. Porosity after die attach cure is always a curial factor which affects the modulus and conductivity of the device. Investigation on porosity of cured die attached materials was carrying out on different die size range from 0.5mm × 0.5mm to 5mm × 5mm. This helped to understand the effect of die size on sintering process. Optimization of dispensing pattern and die attach process challenges of thin die attachment were discussed in details in this paper.
机译:在本文中,讨论了两种类型的高导电性银浆芯片贴装材料的芯片贴装工艺特性。第一种银浆芯片固模材料(DA1)被用作参考,它是载银的环氧粘合剂,具有60W / mK的高导热率和16Ms / m的电导率。可以在低压或无压下于220°C至280°C的温度下烧结第二种银浆芯片附着材料(DA2)。 DA2材料具有100–170W / mK的高导热率范围和12–15Ms / m的电导率范围。工艺规格设置为:芯片倾斜度<1%,平均键合线厚度在25μm至50μm之间,并且完全覆盖芯片附着材料,而不会在芯片表面上溢出材料。针对两种银浆材料,在镀银的QFN引线框架上使用70μm的薄硅菊花链芯片(芯片尺寸为5mm×5mm)进行了工艺优化,并达到了所需的工艺规格。在DA1上优化的工艺实现了24.5μm至30.5μm的平均键合线厚度,芯片倾斜度小于0.24%,DA2的平均键合线厚度在32.6μm至44.2μm的范围内,芯片倾斜度小于0.15%。对于固定厚度为5mm×5mm的不同厚度(使用了50μm,70μm和175μm)的不同厚度的银烧结浆料,在裸片附着工艺上还有进一步的评估。管芯附着固化后的孔隙率始终是影响该器件的模量和导电率的关键因素。在0.5mm×0.5mm至5mm×5mm的不同模具尺寸范围内对固化的模具附着材料的孔隙率进行了研究。这有助于了解模具尺寸对烧结过程的影响。本文详细讨论了分配模式的优化和薄芯片附着的芯片附着工艺挑战。

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