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Die backside Stress modification by coating of Si3N4 or AIN layers

机译:通过涂覆Si3N4或AIN层来改变芯片背面的应力

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摘要

The ability to improve the mechanical properties of a microelectronic package, including reducing the thermal- mechanical stress and increasing the die breaking strength is a long-sought goal in electrical assembly and packaging technology. Failure modes related with die backside stress caused by warpage or cosmetic defects may occur without a well control of die-backside stress. In this study, the modifications of die backside stress by coating of a thin layer of AIN or Si3N4 have been investigated. The simulation through the Finite Element Method (FEM) indicated that the stress distribution can be modified after coating and it is strongly related to the thickness of the coated layer, as the stress of die backside surface reduces. Die breaking strength has been measured by 3 point bending test and the measurement results are compared between samples with and without coatings. It is demonstrated that the die breaking strength is related with the thickness and the surface roughness of the coating layer of AIN or Si3N4. Improvement in the die breaking strength can be realized when the thickness and surface roughness are both optimized. The results suggested the additional coating of the die backside may be a feasible way to improve the mechanical properties of the electronic packages.
机译:改善微电子封装的机械性能(包括降低热机械应力和增加芯片断裂强度)的能力是电气组装和封装技术的长期目标。如果没有很好地控制芯片背面应力,可能会发生与翘曲或外观缺陷引起的芯片背面应力有关的失效模式。在这项研究中,已经研究了通过涂覆AIN或Si3N4薄层来改变芯片背面应力的方法。通过有限元方法(FEM)进行的仿真表明,应力分布可以在涂覆后进行修改,并且随着模具背面表面应力的减小,应力分布与涂层的厚度密切相关。通过3点弯曲试验测量了模具断裂强度,并且比较了有涂层和无涂层的样品之间的测量结果。结果表明,模头断裂强度与AlN或Si 3 N 4涂层的厚度和表面粗糙度有关。当同时优化厚度和表面粗糙度时,可以提高模头断裂强度。结果表明,芯片背面的额外涂层可能是改善电子封装机械性能的可行方法。

著录项

  • 来源
  • 会议地点 Xiamen(CN)
  • 作者单位

    State Key Laboratory of Electronic Thin films and Integrated Devices, University of Electronic Science Technology of China, Chengdu, Sichuan 610054, P. R. China;

    State Key Laboratory of Electronic Thin films and Integrated Devices, University of Electronic Science Technology of China, Chengdu, Sichuan 610054, P. R. China;

    State Key Laboratory of Electronic Thin films and Integrated Devices, University of Electronic Science Technology of China, Chengdu, Sichuan 610054, P. R. China;

    State Key Laboratory of Electronic Thin films and Integrated Devices, University of Electronic Science Technology of China, Chengdu, Sichuan 610054, P. R. China;

    Intel Products (Chengdu) Ltd. No. 8-1 Kexin Road, Chengdu High-Tech Zone (West Park),Chengdu, Sichuan 611731,P. R. China;

    Intel Products (Chengdu) Ltd. No. 8-1 Kexin Road, Chengdu High-Tech Zone (West Park),Chengdu, Sichuan 611731,P. R. China;

    Intel Products (Chengdu) Ltd. No. 8-1 Kexin Road, Chengdu High-Tech Zone (West Park),Chengdu, Sichuan 611731,P. R. China;

  • 会议组织
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类 TN405.94;
  • 关键词

    flip-chip; coating layer; stress modification; FEA; 3PB;

    机译:倒装;涂层;应力改性; FEA; 3PB;

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