A mixed style multiplier architecture for low dynamic and leakage power dissipation

摘要

In this paper a new technique for the design of combinational circuits for low power is introduced. The basic idea is to bypass blocks of logic when their function is not required, using low delay and area overhead components (transmission gates). While this technique offers great dynamic power savings mainly in array multipliers, due to their regular interconnection scheme, it misses the reduced area and fast speed advantages of tree multipliers. Therefore, a mixed style architecture, using a traditional, tree based part, combined with a bypass, array based part, is proposed. Through extensive experimentation it has been found that while the bypass technique offers the minimum dynamic power consumption value, the mixed architecture offers a delay*power product improvement ranging from 1.2x to 6.5x, compared to all other architectures. Furthermore, the tree part of the mixed architecture has enough timing slack to be implemented with high Vth low leakage components, offering an extra 20%–30% leakage power saving, which is a considerable value in deep submicron technologies.