Modeling Evolution of Temperature, Stress, Defects, and Dopant Diffusion in Silicon During Spike and Millisecond Annealing

摘要

The bulk CMOS devices continue to be the dominant player for the next few technology nodes. This drives the increasingly contradicting requirements for the channel, source/drain extension, and heavily doped source/drain doping profiles. To analyze and optimize the transistors, it has become necessary to simultaneously analyze effects that have been previously decoupled. The temperature gradients, combined with stress engineering techniques such as embedded SiGe and Si:C source/drain and stress memorization techniques, create non-uniform stress distributions which are determined by the layout patterns. The interaction of implant-induced damage with dopants, stress, and defect traps defines the dopant activation, retention of useful stress, and junction leakage. This work reviews recent trends in modeling these effects using continuum and kinetic Monte Carlo methods.