Trace-Driven Hybrid Simulation Methodology for Simulation Speedup Rapid Evaluation of a Pipelined Processor

摘要

This paper proposes a rapid evaluation scheme for cycle counts of a pipelined processor using hybrid simulation technique. A performance model for the simulation consists of both an analytic model and a simulation one, which takes all hazard types of pipeline architecture into consideration. The analytic model reflects structural and data hazards; the simulation model deals with control hazard. A performance simulator for pipeline architecture has been developed through which greater speedup has been made compared with other approaches in evaluation of cycle counts.