Improved 3-D Hierarchical Interconnect Capacitance Extraction for the Analog Integrated Circuit

摘要

The hierarchical block boundary element method (HBBEM), which can extract the whole interconnect capacitance matrix with once computation, is of very high efficiency. In analog integrated circuit layout, the feature size varies largely in different layers. According to this, we present an improved HBBEM in this paper, including a new hierarchical partition method of 3-D blocks, the nonuniform partition of boundary elements and the improved algorithm organization. Numerical results show that the new algorithm is several times faster than the original HBBEM and suitable for the capacitance extraction of real analog integrated circuit, with high accuracy as well.