首页> 外国专利> SEMICONDUCTOR DEVICE WITH REDUCED PARASITIC CAPACITANCE OF PAD TO IMPROVE INPUT IMPEDANCE CHARACTERISTIC WHEN HIGH FREQUENCY SIGNAL IS INPUTTED OR OUTPUTTED IN ANALOG INTEGRATED CIRCUIT

SEMICONDUCTOR DEVICE WITH REDUCED PARASITIC CAPACITANCE OF PAD TO IMPROVE INPUT IMPEDANCE CHARACTERISTIC WHEN HIGH FREQUENCY SIGNAL IS INPUTTED OR OUTPUTTED IN ANALOG INTEGRATED CIRCUIT

机译:当在模拟集成电路中输入或输出高频信号时,具有减小的PAD寄生电容以改善输入阻抗特性的半导体器件

摘要

PURPOSE: A semiconductor device with reduced parasitic capacitance of a pad is provided to improve an input impedance characteristic when a high frequency signal is inputted/outputted in an analog integrated circuit by reducing parasitic capacitance formed between an input/output pad and a ground. CONSTITUTION: A field oxide layer(74), the first insulation layer(76), the first metal layer, an interlayer dielectric(78), the second metal layer(80), a passivation layer(82) and an input/output pad(84) are sequentially stacked on a semiconductor substrate(70) of the first conductivity type. The first metal layer is not formed under the input/output pad. An impurity region which is of the second conductivity type and is electrically floated is formed in the vicinity of the surface of the semiconductor substrate corresponding to the input/output pad.
机译:目的:提供一种具有减小的焊盘的寄生电容的半导体器件,以通过减小在输入/输出焊盘与地之间形成的寄生电容来提高在模拟集成电路中输入/输出高频信号时的输入阻抗特性。组成:场氧化层(74),第一绝缘层(76),第一金属层,层间电介质(78),第二金属层(80),钝化层(82)和输入/输出垫(84)顺序地堆叠在第一导电类型的半导体衬底(70)上。在输入/输出焊盘下方未形成第一金属层。在与输入/输出焊盘相对应的半导体衬底的表面附近形成第二导电类型的并且电浮动的杂质区域。

著录项

  • 公开/公告号KR100448085B1

    专利类型

  • 公开/公告日2004-12-03

    原文格式PDF

  • 申请/专利权人 SAMSUNG ELECTRONICS CO. LTD.;

    申请/专利号KR19970019800

  • 发明设计人 HAM SEOK HEON;

    申请日1997-05-21

  • 分类号H01L23/28;

  • 国家 KR

  • 入库时间 2022-08-21 22:06:17

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