AN INTEGRATED WAFER-SCALE PACKAGING PROCESS FOR MEMS

摘要

Packaging is well known to impose significant cost, performance and fabrication constraints on MEMS devices. We have developed a wafer-scale, integrated packaging process which enables a released MEMS device to be sealed within a thick layer of epi-polysilicon. This encapsulation may be tailored to withstand conventional dicing saws, pick/place chip handling equipment, and even high-pressure injection molding for plastic DIP packages. This architecture can be adapted to a variety of MEMS devices, and is compatible with integrated electronics. This paper will describe this packaging technique and discuss applications.