HARDWARE/SOFTWARE TRADEOFFS FOR IP-OVER-ATM FRAME REASSEMBLY IN AN INTEGRATED ARCHITECTURE

摘要

This paper investigates hardware/software implementation tradeoffs in the reassembly of cells for IP-over-ATM on an integrated architecture combining processing, memory, and embedded direct-memory-access (DMA) engines for the sources and sinks of communication traffic. Two approaches are considered. In the first approach, CRC computation is performed in software. In the second approach, CRC computation is offloaded to a specialized module embedded in one of the DMA engines. The two alternatives are evaluated through simulated execution of representative control software with detailed modeling of cache/memory effects and bus contention. The results indicate that the software-CRC approach can support OC-3 rates with a 333MHz processor, and the hardware-CRC approach can support OC-3 rates with a 71MHz processor and OC-12 rates with a 333MHz processor.