FEDRAM: A CAPACITOR-LESS FERROELECTRIC DRAM CELL

摘要

A capacitor-less DRAM cell based on ferroelectric-gate memory transistor structure is proposed. As shown in Fig.l, the basic structure of the new DRAM cell is very similar to a conventional MOSFET, with the gate oxide replaced by a ferroelectric film sandwiched between two ultra-thin insulating buffers. In principle, the two buffer layers are not necessary. The two memory states are distinguishable by the two polarization states of the ferroelectric film, which can be altered by a gate voltage pulse of proper polarity, and sensed by the source-to-drain current. We call this new DRAM cell the FErroelectric DRAM, or FEDRAM cell. We note that this structure is similar to a nonvolatile ferroelectric memory transistor, although there are important differences that will be summarized later. The FEDRAM cell has the following major advantages compared to the conventional DRAM cell: 1. The FEDRAM cell size is inherently smaller because it does not require a storage capacitor. It is also much more scalable in the future. 2. Because of the non-destructive readout scheme of the FEDREM, and its much longer retention time, a much longer time between refresh can be tolerated. 3. It is much more amenable to imbedded applications, because of the absence of the storage capacitor. Compared to the non-volatile ferroelectric memory transistor, on the other hand, the FEDRAM is a lot more manufacturable, because of its much shorter memory retention requirement and its tolerance for much greater gate leakage current. The feasibility of the FEDRAM concept may be demonstrated by some preliminary results below. Figure 2 shows a schematic representation of the FEDRAM gate capacitor used in this study. Here the ferroelectric SBT film (～250 nm thick) is deposited by the spin-on method with a MOD solution, the silicon nitride buffer layer (< 2 nm) is deposited by the JVD method, and the Au Electrode is deposited by thermal evaporation. Figure 3 shows the C-V curves of a FEDRAM gate capacitor with an N-type Si, in which the hysteresis is due to the polarization of the ferroelectric SBT film. Figure 4 shows the zero-bias capacitance of the FEDRAM capacitor after the application of a single pulse of various pulse widths. One can see that the switching from low to high capacitances has taken place even with the shortest pulse available for the experiment; i.e., within 8 ns. Figure 5 shows the retention characteristic of a FEDRAM capacitor after a gate-pulse, indicating that it retains more than 50% of its maximum value even after 5 minutes. We are collaborating with other institutions to fabricate FEDRAM transistors, and will present the transistor results if they become available at the time of the conference. We would like to thank Xin Guo for depositing the JVD silicon nitride buffer layer used in this study.